High-level, graphical design tools are often used in the design of programmable logical devices (PLDs) such as field-programmable gate arrays (FPGAs). For example, System Generator for DSP® available from Xilinx, Inc., runs within the modeling environment of Simulink® available from The MathWorks, Inc. and can be used to express, simulate and synthesize control and digital signal processing (DSP) algorithms embodied as primary logic components within field programmable gate arrays (FPGAs). However, in existing design environments, it is necessary to employ comparatively tedious hardware description languages (HDL) such as Verilog® and VHDL® in order to implement infrastructure and off-chip input-output (I/O) interfaces. This involves, for example, the detailed specification of interface circuitry, as well as the configuration of impedances, drive levels, phase delays, supply voltages and the clocking schemes and timing offsets of specialized subcircuits associated with clock management, busses, and other off-chip input-output (I/O) functions.
HDL design environments needed to specify infrastructure and off-chip I/O characteristics, have also traditionally served as the “top-level” or master design environment for PLD design flows. It is within the top-level design environment where the merging of infrastructure subcircuits with the machine-generated logic produced by the high-level, graphical design tools occurs.
It has therefore been necessary that application and domain experts who use the high-level, graphical design tools maintain competency with HDL design environments in order to generate a final PLD image and verify the resulting design in-circuit. This maintenance of competency has been necessary because during the development of PLD application it may frequently be necessary to implement and deploy prototypical designs, not only to verify primary logic components, but also to provide in-circuit test harness for additional system elements that are external to the PLD, and to verify communication schemes between the PLD and other attached hardware.